Data carried over a number of tributaries such as DS1, DS3, E1, E3, etc., each of generally different frequencies, may be multiplexed together so that it can share a common transmitter, receiver and transmission media. In order to transmit such data together, it is mapped onto a frame at the place where it enters the network. All of the signals from the various tributaries are synchronized to a single network clock. Excess bandwidth is filled with stuff bits which carry no information. A pointer adjustment can be used in place of or, in addition to, the stuff bits to indicate changes in the data rate of the synchronous channel and lack of synchronism of the nodes in the network. At the other end of the network a desynchronizer reads and transmits asynchronous data that had been carried over the synchronous channel. Variations in the instantaneous rate of the payload data caused by the interspersing of overhead data and the stuff bits can give rise to payload mapping jitter which can feed through into the desynchronizer output. The pointer adjustment due to lack of synchronism of the nodes in the network gives rise to another form of jitter which is more serious than mapping jitter. One pointer adjustment results in 8 cycles of network clock jitter. The pointer adjustment occurrence is a stochastic process and, as a result, it is difficult to predict its behaviour. Desynchronization is used at the destination of the digital signals to also attenuate the mapping jitter. Mapping jitter is deterministic and easy to filter even with wide bandwidth phase locked loop (PLL) circuits.
Desynchronizers typically include a first in first out buffer (FIFO), a phase detector to measure the FIFO buffer depth, a passive or active analog loop filter to filter the phase detector output, and a voltage controlled oscillator (VCO) to generate an output clock to control data transmission from the FIFO buffer. These elements make up a phase locked loop.
There are some important differences in the way single and multiple channel desynchronizers are designed. The term “multiple channel” means that more than one data signal is being dropped or extracted from the SONET/SDH signal. For example, in the case of the OC-1 signal one can drop 28 DS1 signals, which might need to be desynchronized. In the case of the OC-3 signal one can drop 3 DS3 signals or 84 DS1 signals. In the case of the OC-12 one can drop up to 12 DS3 signals or 336 DS1 signals. With the advance of data communications and the requirement for higher bandwidths, there are more and more instances of multiple channels being dropped from the same SONET/SDH signal.
A multiple channel desynchronizer should not use a voltage-controlled oscillator (VCO) to generate the desynchronized output clock. Most of the known desynchronizers use voltage-controlled crystal oscillators (VCXOs) or VCOs in cases where desynchronizers produce a control voltage that controls the frequency of the VCO. Multiple channels, for example 12 channels of DS3 can be dropped from OC12, can have output frequencies quite close to each other and, as a consequence, mutual coupling can cause excessive jitter. The reason for the excessive jitter is caused by the large index of modulation of the frequency modulation device. The index of modulation of the frequency modulation device is inversely proportional to the frequency of modulation. Thus, small frequency offsets between desynchronized clocks, if there is even a very small coupling between the desynchronization circuits, would produce through PLL action very low modulation frequencies on the control voltages which would modulate, excessively, the VCO outputs.
The multiple channel desynchronization circuit should use a phase modulation method when generating desynchronized clocks to avoid the excessive jitter caused by mutual coupling of output clocks. The phase modulation device can be implemented as an endless phase modulator, a numerically controlled oscillator (NCO) or a single side-band modulator (SSB). Several patents have already suggested use of the NCO devices for the desynchronization. However, a large number of the NCO devices on the same chip, especially if generating high frequencies, would result in large power consumption. A better way, as far as power consumption is concerned, where an NCO is used to synthesize a low frequency, is to up-convert this low frequency using a mixer and a high frequency local oscillator (LO). The output signal from the mixer is filtered using the LC filter. In an ASIC implementation of the desynchronizer use of the LC filter is not an option. More suited for the ASIC implementation is a version of up-conversion implementation, which uses the SSB modulator. By the careful matching of phases and amplitudes in two branches containing double balanced mixers, the SSB modulator suppresses unwanted products of mixing, the LO leakage and the undesired side-band. Normally, the SSB modulators can suppress the unwanted products by more than 20 dBs, resulting in jitter of less than 0.05 UIpp. The SSB modulation results in intrinsic jitter well below the level allowed by Bellcore GR-253-CORE. Some care has to be taken to avoid excessive mutual coupling of output clocks because they still add to jitter, although there is no excessive problem with low frequency offsets as in the case of the frequency modulation device.
The preferred implementation would use an endless phase modulator, because it is a digital approach and it is robust, due to the fact that coupling between different output signals has the least effect.
The second conclusion from investigating a multiple channel desynchronizer is that a separate desynchronizer for each channel will result in an extremely large circuit size. That is specifically true if each of the necessary steps to be performed are implemented without the re-use of circuitry. None of the prior art discloses the re-use of the circuitry. Accordingly, it is an object of the invention to merge the desynchronization of all channels into a single channel by re-using the desynchronization circuitry.